1. Technical Field
The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to a system and method for generating constraint preserving testcases in the presence of dead-end constraints.
2. Description of Related Art
A typical integrated circuit interacts with its design environment. During simulation-based functional verification, the design environment is modeled by a testbench. The modeling of design environments using constraints has gained widespread industrial application and most verification languages include constructs for specifying such constraints. Constraints confine simulations of a circuit design to a legal input space by specifying conditions that must hold in any state explored by a verification algorithm. Semantically, the verification tool must discard any states for which a constraint evaluates to a 0, i.e. the verification tool may never produce a failing scenario showing a violation of some property of the design.
Although constraints enable efficient modeling of design environments, they pose several challenges to verification algorithms. Constraint preserving testcase generation has been widely researched (see for example, the SimGen verification tool described in “Modeling Design Constraints and Biasing in Simulation Using BDDs,” J. Yuan et al., ICCAD 1999). These solutions, however, do not address preservation of dead-end constraints which entail states for which there is no legal input stimulus. Such dead-end constraints cause simulation states that cause the verification tool to not be able to continue the verification process. Dead-end constraints tend to reduce the efficiency of explicit-state analysis as well as semi-formal analysis. When a dead-end state is reached, the only recourse is to backtrack to an earlier state.
Dead-end constraints are typically treated as user errors in known methodologies, such as in the SimGen verification tool. As such, it is left up to the user to fix the dead-end constraint problem such that there are no more dead-end states encountered. As a result, simulation pattern generation mechanisms for verification tools suffer from being highly ineffective under dead-end constraints.